A dynamic random access memory (DRAM) that is a memory used in a storage device needs refreshing to prevent loss of data stored in memory cells. This refresh should be performed at prescribed intervals. Meanwhile, a synchronous DRAM (SDRAM) that is a kind of DRAM has a ZQ calibration function to increase the waveform quality of a control signal. This is a function to dynamically correct a termination resistor inserted into a signal line for impedance matching even in a case where the impedance of the signal line changes due to a rise in ambient temperature or the like. Like refresh, calibration for performing this correction also needs to be performed at prescribed intervals.
However, these processes require longer periods of time than memory access for a data write/read process. Also, any memory access cannot be made during these processes, and therefore, the load on the arbiter that conducts arbitration of processes for a storage device, including memory access, becomes larger.
To counter this, there is a suggested data processing system that performs control so that refresh and calibration will not occur in succession (see Patent Document 1, for example). This is to perform control so that any command for requesting a process related to refresh or calibration will not be issued for a certain period of time after a command for requesting a process related to the other action between refresh and calibration is issued.